1. Field of the Invention
The present invention relates to a method for bypassing a plurality of clock trees in an EDA tool (electronics design automatic tool), and more particularly, to a method for using timing simulation and authentication software of an EDA tool to bypass a plurality of clock trees in the EDA tool.
2. Description of the Prior Art
In the current chip-design industry, due to the abundance of CAD tools, EDA tools for designing various electronic ICs have matured. For each process of IC design, there are specific and appropriate EDA tools provided for the chip developers.
Please refer to the FIG. 1. FIG. 1 is a flowchart of the digital circuit design process of the prior art. Generally, the process of the digital circuit design can be divided into the establishment of specification and structures, the design and identification of the RTL (register-transfer level), the design and certification of the Gate-Level, and the design and simulation of the electric circuit layout.
Regarding the process of the establishment of specification and structures, just as its name implies, the process sets some important specifications, functions, and parameters of the desired object before developing a digital circuit. The main purpose of the design and identification of RTL is to express the behaviors of the digital logic circuit. Regarding the concrete way of how to express, the currently popular method is to implement the steps that describe the logic behaviors of the digital circuit with a hardware description language (HDL) that is very similar to a general software programming language. After completing HDL programming, the HDL will be immediately compiled to a high-level logic electric circuit with a corresponding compiler. Because that the HDL can be easily modified, revised, and enlarged with more functions, its functions have become an industry standard. Take VHDL and Verilog, two of the most popular HDLs, for example. They have become industry standards after repeated corrections. Regarding the design and certification of the Gate-Level, the high-level logic electric circuit will be further converted to the low-level logic electric circuit. For example, a full adder will be converted to a plurality of XOR, OR, and AND Gates. Regarding the final process of the design and simulation of the electric circuit layout, an electric circuit layout auto-creation program will create an electric circuit layout diagram. For example, the program “Cadence Ensemble” can convert the low-level logic electric circuit of the Gate-Level to the electric circuit layout diagram. The electric circuit layout diagram will be sent to a wafer factory for carrying out chip production after passing through some testing and confirmation procedures.
For ensuring the quality of the manufactured chips, careful simulations and tests are necessary in each process. Therefore, the process of the RTL, the Gate-Level, and the design and simulation of the electric circuit layout respectively have their own specific simulation and identification programs. In addition, the lower-level process is closer to the actual chip operating conditions, and the corresponding simulation and identification programs have to be more sophisticated and precise. For example, in the process of the RTL, the parameters can be roughly decided with the delay time of the high-level logic elements, and the parameters usually can be roughly programmed as ideal values under most of conditions. However, in the process of the Gate-Level or even in the process of the design and simulation of the electric circuit layout, the simulation and identification programs have to consider single logic gages, or even a parameter of a transistor and the delay time of a metal wire.
In order to ensure that the chip can operate well in the four limiting corners during the semiconductor manufacturing process, the chip developers have to make sure the “margin” is large enough for “timing”, and the key lies in the synchronization of the clock signal. That is, the clock signal should be in phase. The system usually comprises a main transmission line, and the main clock signal is transmitted toward each independent area of the chip by a plurality of branch transmission lines connected with the main transmission line. Since part of the independent areas will operate with the main clock, such as raising or decreasing the frequency of the main clock, and the transmission line will cause the signal delays, the phase of each clock signal in each branch transmission line will be a little different. The non-synchronizing effect critically influences the digital circuits that require extremely precise timing. Therefore, the synchronization between the main clock signal and each branch clock signal is essential. The EDA tool of the present invention can make use of the results of the timing simulation and authentication to synchronize the devices that require synchronization. The EDA tool will slightly adjust those devices with a laggard clock or a transcended clock. For example, installing a buffer in the metal wire that transmits the clock signal will cause a little delay of the clock signal transmitted in the transmission line, or shortening the metal wire can shorten the transmission time of the clock signal. All the above-mentioned methods are based on the fact that the timing simulation and authentication software can precisely measure all the timing data.
However, most other current timing simulation and authentication software cannot bypass some devices that comprise the clocking device such as a flip-flop or a latch. The phenomenon of “non-bypass” will cause the result that the synchronization of the EDA tool will be limited only in the input port of the clocking device, and the synchronization of the clock signals in the other branch devices behind the clocking device cannot be achieved at the same time with the synchronization of the clocking device. The synchronization has to be performed in each branch device respectively. This effect is harmful to the large-scale digital circuits that comprise numerous clocking devices and branch devices.
Recently, although there are a few EDA tools that can bypass the clocking devices during the process of the timing simulation and authentication, chip developers have to pay extremely high prices obtain this function.